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UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
16/107,942 08/21/2018 Nuo Xu 146114/414467-00010 6924
129498 7590 08/24/2021
Lewis Roca Rothgerber Christie LLP
P.O. Box 29001
Glendale, CA 91209-9001
EXAMINER
CHIN, EDWARD
ART UNIT PAPER NUMBER
2813
NOTIFICATION DATE DELIVERY MODE
08/24/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PLPrivatePair@lrrc.com
pto@lewisroca.com
PTOL-90A (Rev. 04/07)
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UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NUO XU, FAN CHEN, WEIYI QI, JONGCHOL KIM,
JING WANG, YANG LU, and WOOSUNG CHOI
Appeal 2020-005920
Application 16/107,942
Technology Center 2800
Before JEFFREY B. ROBERTSON, JAMES C. HOUSEL, and
CHRISTOPHER C. KENNEDY, Administrative Patent Judges.
HOUSEL, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 11, 12, 14–18, and 20. Pending claims
1–10, 13, and 19 are not before us on appeal.2 We have jurisdiction under
35 U.S.C. § 6(b).
1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies Samsung Electronics Co., Ltd. as the real
party in interest. Appeal Brief (“Appeal Br.”) filed March 23, 2020, 1. 2 The Examiner has withdrawn pending claims 1–10 from consideration as
directed to a non-elected invention, and has objected to pending claims 13
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Appeal 2020-005920
Application 16/107,942
2
We REVERSE.
CLAIMED SUBJECT MATTER
The invention recited in the claims on appeal relates to methods for
wafer map analysis, in particular for defect detection and analysis in the field
of semiconductor device fabrication. Specification (“Spec.”) filed August
21, 2018, Title and ¶ 2.
3 Appellant discloses that the integrated circuits
(“ICs”) of the dies formed on a semiconductor wafer are typically tested
after fabrication. Id. ¶ 4. In such testing, Appellant discloses that a wafer
prober may be used to test the functionality and performance of each die on
the wafer, whereby the dies are classified based on performance. Id.
Appellant discloses “methods for generating full wafer maps showing
predicted classifications of dies of a wafer without testing all of the dies on
the wafer.” Id. ¶ 5.
Claim 11, reproduced below from the Claims Appendix to the Appeal
Brief, is illustrative of the claimed subject matter:
11. A method for reconstructing wafer maps of
semiconductor wafers comprising a plurality of dies,
comprising:
receiving, by a processor, test data of characteristics of
dies at sparse sampling locations of a semiconductor wafer, the
sparse sampling locations being selected based on a probing
mask; and
and 19 as reciting allowable subject matter, but depending from rejected
claims. Final Office Action (“Final Act.”) dated December 12, 2019, 1, 2,
and 6.
3 This Decision also cites to the Examiner’s Answer (“Ans.”) dated July 7,
2020, and the Reply Brief (“Reply Br.”) filed August 13, 2020.